244 Timing Analysis

The basic clock cycle model is:

Tmax + Tsetup + Tskew + Tclk−to−Q ≤ T

- Tmax = time to propagate through the gates,

- Tsetup = time for signal to be stable within a cycle (before a clock tick)

- Tskew = mis-alignment of a clock signal to FF's

- Tclk-to-Q = time to change FF's output

in additional, there is the hold constraint:

Tmin ≥ Thold + Tskew

- Thold = time for signal to be stable within a cycle (after a clock tick). This says we have to hold the input signals to FFs for a while after a clock tick.

Tsetup is how fast a FF can operate (sufficient condition). Thold is the minimum time a FF need to operate (necessary condition). If Tsetup ≥ Thold, then we can ignore Thold.

Timing analysis helps to automatically infer the clock cycle time to run the circuit. It needs to model delay for wires and gates.